The operational mechanism of a 2-bit synchronous counter is as follows įigure 8.4-a 2-bit synchronous binary counter In order to fully comprehend the operation of this type of counter, we need to be it bear in mind that when positive edge of a clock pulse strikes, flip-flop tend to toggle at that time. It means that FF1 flip-flops change its state only when normal output of FF0 flip-flop is binary 1. However, J 1K 1 input of FF1 flip-flop is controlled with FF0 flip-flop’s normal output Q 0. Therefore, whenever clock pulse is received, first flip-flop of this counter changes its state just similar to the first flip-flop of a ripple counter. According to the diagram, only input J 0K 0 of the first flip-flop FF0 has been connected with binary 1 or high, so that the flip-flop may operate consistently. It is obvious from the figure that every flip-flop has been receiving an equivalent clock pulse, as result of which, both flip – flops change their state simultaneously. In figure 8.4, a 2-bit synchronous binary counter has been represented, which consists of two JK flip-flops and a series of clock pulses. As such, its speed is low (as compared to a synchronous counter) as a result of a high overall propagation delay time. Further, total propagation delay time of a ripple counter is equal to the sum of individual propagation delay time of all flip-flops existing within the counter. As all flip-flops in a ripple counter are not coherent or synchronized with a common clock pulse or these flip-flops are not controlled via a common pulse, therefore ripple counter is also known as an asynchronous counter. The effect of these pulses is felt on all flip-flops in a serial fashion. Whereas pulses coming from clock (which are desired to be calculated) are only exerted on the first flip-flop. We know that in asynchronous or ripple counters (which have been discussed above) all flip-flops have been inter-connected in a manner that output of one flip-flop becomes input for another other flip-flop. Therefore, as a result of a low propagation delay time of this counter (relative to an asynchronous counter), its counting speed is higher. As all flip-flops of such counters operate together due to a parallel clock pulse, or they change their states all together, therefore circuit’s overall propagation delay time is equivalent to the propagation delay time of just one circuit. Therefore, these types of counters are also called parallel counters. Remember that all flip-flops are connected together in a parallel fashion with respect to the clock pulse in such types of counters, owing to which, an equal clock pulse is received on all flip-flops. coherent with a single clock pulse) through a common clock pulse (which is required to be counted), are called synchronous counters. In other words, counters where in all flip-flops are synchronized or harmonized (i.e. all flip-flops clocks are controlled simultaneously by means of a single clock pulse or every flip-flop receives an equivalent clock pulse). The synchronous counter is a counter where in all clocks inside flop-flops are shorted (i.e.
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